1. Related Applications
This application is related to application Ser. No. 07/994,402, now U.S. Pat. No. 5,394,556 entitled "Method and Apparatus for Unique Address Assignment, Node Self-Identification and Topology Mapping for a Directed Acyclic Graph" and Ser. No. 07/994,128, now abandoned entitled "Method and Apparatus for Transforming an Arbitrary Acyclic Topology Collection of Nodes into an Acyclic Directed Graph" each of which is assigned to the assignee of the present application and filed concurrently herewith.
2. Field of the Invention
The present invention relates to computer systems. More particularly, the present invention relates to a method and apparatus for establishing and utilizing a communications scheme between a plurality of arbitrarily assembled elements of a computer system.
3. Background
Components within a given computer system need the ability to convey signals amongst themselves. In very simple systems, it is possible to have each element of the system directly wired to all of the other parts of the system. However, in reality, in order to make computers expandable and to accommodate an unknown number of system parts, computer architects long ago developed the concept of a communications bus.
A bus is a communications path, such as a wire or wires, running throughout the computer system. Each component of the system need only plug into the bus to be theoretically connected to each of the other components in the system. Of course, each component cannot simultaneously communicate with other components because there may be only a single communications channel between the components. It is necessary when utilizing a communications bus to establish some form a sharing arrangement so that each component may use the bus to communicate with other components in an efficient manner that does not leave critical pieces of information from one component hanging, waiting for bus access. The method by which components on the bus share the bus is generally referred to as a bus arbitration scheme.
In addition to the critical need to optimize the bus arbitration scheme so as to maximize the flow of important information, the physical (and logical/electrical) configuration of the bus itself can and should be optimized to minimize system delays while remaining as flexible as possible.
In order to communicate with other components attached to a bus, each component must be equipped with hardware such as transmitting and receiving circuitry compatible with the communications protocol implemented for the bus. One such communications standard is described in IEEE Standards Document P1394 entitled "High Performance Serial Bus", said document attached as Appendix A to this document. The standard described in P1394 is intended to provide a low cost interconnect between cards on the same backplane, cards on other backplanes, and external peripherals.
Prior art buses or networks required knowing what was being plugged in where. For example, the back of many computers have specified ports for specific peripherals. Some computers implement several buses, such as the Macintosh which uses a bus referred to as ADB for components like a mouse and keyboard and SCSI bus for other peripherals. These types of buses provide for daisy chaining elements together but connections are of limited topology. Other known buses/networks require that the nodes of the network be arranged in a ring, a loop which must be closed in order to operate. Finally, star, or hub-and-spoke arrangements required that each node be directly linked to a central master. Each of the prior art systems lacks a desirable measure of flexibility.
It would be desirable, and is therefore and object of the present invention, to be able to arbitrarily assemble elements of a computer system onto a bus where the arbitrary topology can be resolved by the system into a functioning system without requiring a predetermined arrangement of components.